When a printed circuit (PC) board has selective areas intended to have gold on them, the manufacturer may face significant challenges with its gold plating processes. In most cases, features requiring gold finish are first attached to plating rails, as shown by way of example in FIG. 1. PC board 10 has surface copper features, such as fingers 14a-14d, which are to be finished with gold; it also has surface copper features, such as tabs 12a-12c, which are to be finished with gold, as well. In a standard process, connecting busses 20a-20e must be patterned as additional surface copper features on PC board 10 and plating rail 18 is connected to them. Extraneous copper is then etched away, leaving behind all the copper features shown in FIG. 1, namely tabs 12a-c, fingers 14a-d, busses 20a-e and plating rail 18. PC board 10 is then placed in an electroplating bath containing gold. Plating rail 18 is then electrically charged at a negative potential, whereas the bath is electrically charged at a positive potential. Since all the copper features on PC board 10 are electrically connected to plating rail 18, gold is deposited, or coated, on all the copper features. The plating rail and the busses are then removed by mechanical means, such as cutting or routing off the board. In this manner, good quality gold finish is produced on the PC board.
The above described process may not be used, however, when a plating rail or its associated busses cannot be patterned on the PC board. In this case, the PC board manufacturer has two options: (1) electroplate gold before etching copper, or (2) use electroless plating to deposit gold after the extraneous copper has been etched away. Each of these options will now be described with reference to FIGS. 2 and 3.
Multilayer circuits normally consist of two or more layers of separate and different circuit patterns which have been laminated together under heat and pressure to produce a strong multilayer PC board. FIG. 2 shows a small cross section of PC board 10 illustrating sheets 22a-22d having been pressed together to form a multi-layered board. Inner layers 26b-26d and outer layers 26a and 26e (laminas 26a and 26e) may each contain voltage and ground planes, as well as mounted integrated circuits (not shown) where the planes provide the power connections. Ground and voltage planes of identical configuration may often be employed in several boards having different circuitry patterned to suit the operational requirement of the user. Some boards may contain inner layers composed of circuit patterns with numerous conductors; other boards may contain both circuit patterns and planes as inner layers. The latter are being found increasingly useful in high density packaging that employs integrated circuits.
In order to connect the layers in a multi-layer board, plated-through holes are made. As shown in FIG. 2, through holes 24a and 24b have been drilled in PC board 10. Through a process explained below, the through holes are plated with a metal, such as copper, to form conductor layers 30a and 30b. In this manner, pads 28a and 28b, for example, may be interconnected.
Returning now to option 1, the typical process for electroplating gold before etching copper will be described by referring to FIGS. 3a and 3b. As shown, PC board 10, which has multiple sheets (only sheets 22a and 22b shown), is laminated under heat and pressure to form a multi-layered board. Through holes (only through hole 24a shown) are drilled and cleaned. The following steps are performed next:
a) Electroless copper is deposited to form first copper layer 42. It will be appreciated that copper layer 42 is deposited everywhere, e.g. on top of lamina 26a, on the bottom lamina (not shown), and in all the through holes (only through hole 24a shown). PA1 b) Mask 40 is patterned to protect areas from the subsequent depositions of copper and solder. PA1 c) Second copper layer 44 is electroplated on all areas not protected by mask 40. It will be appreciated that second copper layer 44 forms the pads and busses on lamina 26a and on the bottom lamina (not shown). It will further be appreciated that second copper layer 44 may be electroplated, because of the presence of first copper layer 42. Since first copper layer 42 is formed continuously everywhere on the top and bottom of PC board 10, a plating rail may be formed, as described earlier, thus permitting electroplating. PA1 d) Solder is electroplated next to form etch-resist layer 46. It will be appreciated that tin-lead may also be used as an etch-resist. PA1 e) Next, mask 40 is removed in a standard manner. PA1 f) New mask 50 is patterned prior to gold depositions for protecting areas from the subsequent deposition of gold. PA1 g) Etch-resist layer 46 is stripped from all areas not protected by new mask 50. PA1 h) Gold is electroplated on all areas that previously were stripped. Sometimes a layer of nickel is deposited first and then the gold is deposited on top of the nickel. Although not shown in FIG. 3b, it will be appreciated that a gold layer replaces etch-resist layer 46 in areas external to new mask 50. PA1 i) New mask 50 is now removed (not shown). PA1 j) Finally, copper is etched from the board (not shown). All areas on the board that still have etch-resist layer 46 are protected from copper being etched away. In addition, areas having had gold deposited on them are also protected, because the gold layer also acts as an etch-resist. PA1 a) First copper features for plating gold thereon and second copper features for plating copper thereon are selected on the external surface. PA1 b) The first copper features are internally connected to the second copper features. PA1 c) An etch-resist is deposited on the first and second copper features. PA1 d) The second copper features are masked, while a region containing the first copper features are exposed. PA1 e) Copper is etched from the region. PA1 f) The etch-resist on the first copper features is removed. PA1 g) Gold is plated on the first copper features.
In this manner, gold may be electroplated prior to etching of copper, because all features on the board are still electrically connected. In this case, during a subsequent etching process, the gold serves as an etch-resist in selected areas, while solder or tin-lead serves as an etch-resist on the rest of the board.
Problems arise, however, with the process just described. While gold and solder (or tin-lead) serve as an etch-resist during copper etching, some amount of copper is etched from under the gold and solder layers. This is known as an under-cut phenomenon. While under-cutting is not a problem with a solder layer, because the solder may subsequently be re-flowed, it is a major quality issue with a gold layer. Since the gold cannot be re-flowed, a thin layer of gold may overhang the copper base, and may easily break-off and contaminate the board with conductive gold flakes.
In order to avoid the aforementioned problem, PC board manufacturers may sometimes select another process which uses electroless plating to deposit gold, after the extraneous copper has been etched away. This process does not require an electrical path between surface copper features to be plated and produces a good quality of gold finish, without any gold overhang. The gold electroless plating chemistry, however, is very aggressive and there are no production-quality resists (mask patterning) available to adequately protect copper features, which must remain unplated from being gold plated.
Furthermore, if gold is deposited on copper features that subsequently are exposed to soldering (during component assembly, for example), solder joint quality and reliability are affected. This effect is proportional to the amount of deposited gold. In cases where the amount of gold required is minimal (less than 15 micro-inches), PC board manufacturers may choose to deposit gold everywhere on the board. Solderability may still be affected, but the need to mask off areas on the PC board is eliminated. If the amount of gold required in selected areas exceeds the amount that may be allowable, however, the board must be masked off and this process quickly falls apart due to unavailability of masks.
The deficiencies of the conventional processes to selectively plate gold on surface copper features of a PC board show that a need still exists for a process which can selectively deposit gold on surface copper features after surface etching, thereby avoiding problems with under-cutting, gold overhangs and flake-offs.